1. Field of the Invention
The present invention relates to static random access memory (RAM) cells, and, more particularly, to a reduction in the cell size of static RAMs using four-transistor cells.
2. Description of the Related Art
A conventional four-transistor (4T) RAM cell consists of a two transistor, two resistive-load flip-flop plus two access transistors (known as word-line or pass-gate transistors), such as described in S. M. Sze, VLSI Technology, McGraw-Hill, NY, pp. 473-478 (1983). One characteristic of such a cell is that its circuit diagram requires some type of interconnection cross-over. Given a conventional two-polysilicon 4T static RAM process, which uses a single gate polysilicon (gate poly) layer, the requirement for this interconnection cross-over leads to an asymmetrical layout. In addition to the layout area required for the active circuit elements of this cell, this asymmetrical configuration typically requires the use of significant layout area for at least three contacts as well as added diffusion and polysilicon regions for interconnection purposes.